ASIC Physical Design Engineer Oeiras

ASIC Physical Design Engineer
Oeiras
Oeiras, Distrito de Lisboa, Portugal

Please note this posting is to advertise potential job opportunities. This exact role may not be open today, but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens.

Cisco is seeking ASIC Physical Design Engineers to join our Silicon One Team. As a member of our team, you will work with
- edge silicon technologies and processes to develop
- scale, complex devices, pushing the limits of feasibility.

Why You’ll Love Cisco

We change the World, you will become passionate about your employer and the brand you represent. Everything is converging on the Internet, making networked connections more meaningful than ever before in our lives. Our employees' groundbreaking ideas impact everything. Here, that means we take creative ideas from the drawing board to dynamic solutions that have
- world impact. You'll collaborate with Cisco leaders, partner with mentors, and develop incredible relationships with colleagues who share your interest in connecting the unconnected.

What You'll Do

• Engage in full chip physical implementation, covering the process from RTL to GDSII, and collaborate with Front-End teams to understand design architecture for effective implementation.
• Perform
  - level netlist synthesis (physical synthesis) and execute physical implementation tasks such as floorplanning, placement, Clock Tree Synthesis (CTS), and routing.
• Optimize design for power, performance, and area, and conduct formal verification to ensure design integrity.
• Perform Static Timing Analysis (STA), complete physical verification, and achieve signoff closure.
• Analyze and resolve Electromigration (EM) and IR-drop (IR) issues to meet signoff requirements.

Who You'll Work With

You'll be part of the Cisco Silicon One team, which is at the heart of Cisco’s software and ASIC design efforts. As part of our team, you’ll contribute to the development of our
- generation network devices—Cisco Silicon One.

Who You Are

You are a skilled engineer who has strong communication skills, is
- motivated, and
- organized.

• B. Sc. /M. Sc in Electrical Engineering, Computer Science, or any other relevant field.
• Proven experience in ASIC physical design and verification.
• Knowledge and experience in
  - level synthesis, place, and route, timing closure.
• Knowledge of
  - standard Pn
  R and signoff tools and their capabilities.

Preferred Qualifications:

• Deep understanding of all aspects of Physical construction and Integration.
• Knowledge in Physical Design Verification methodology LVS/DRC.
• Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc. ).
• Understanding of Static Timing Analysis, timing closure, and design constraints.
• Experience in scripting languages like Tcl, Python, Perl.

Message to applicants applying to work in the U. S. and/or Canada:

When available, the salary range posted for this position reflects the projected hiring range for new hire,
- time salaries in U. S. and/or Canada locations, not including equity or benefits. For
- sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses.